*A 300 mm semiconductor wafer patterned using multiple photolithography steps.*

The process used for manufacturing integrated circuits is called *photolithography*, and it involves the etching of a semiconductor wafer on which an integrated circuit is developed. The etching process uses a series of chemical treatments and subsequent cleaning cycles to etch patterns into the surface of a silicon wafer, known as *integrated circuit features* or *nodes*.

When integrated circuits are manufactured, it is important to optimize both the pattern development and cleaning processes in order to ensure the success of the design. This is because of the interactions that occur between the cleaning agents and the features defining the patterns, which can ruin the integrated circuit by causing permanent feature deformations. Preventing these deformations is becoming an increasingly difficult task, because as both the size of the features and the spacing between the features decrease, the forces acting on them become even more significant. If these forces cause the features to touch, the integrated circuit can undergo *pattern collapse*, where the feature shape is permanently bent, pattern integrity is lost, and the integrated circuit is no longer functional.

Unwanted mechanical stresses can be introduced through van der Waals attraction forces, as well as through the surface tension due to cleaning fluid trapped between features (shown below). These forces can cause the features to bend inward, and if the features don’t return to their original shape, pattern collapse occurs.

*The surface tension force (F) due to the cleaning fluid trapped between the two features. Pattern collapse occurs if the features don’t return to their original configuration and remain touching.*

As integrated circuits become smaller, features are also becoming thinner and taller to accommodate the shrinking surface area of the chip, a trend known as *node shrink*. This trend causes designing and cleaning features to become even more challenging, since the forces acting on the features happen on such a small scale and it is much harder to reach between thin, tall features to remove the cleaning fluid.

Tokyo Electron America (TEL) develops tools for the manufacturing of integrated circuits using finite element analysis (FEA). In a previous blog post, “Stick a TV to the Wall Using Gecko Feet”, my colleague Phil described an instance in which the van der Waals forces exerted by gecko feet were harnessed and amplified to create a “tape” called Geckskin™ that is capable of holding a TV to a wall. These researchers used van der Waals forces to their advantage, and they were a vital component in producing the final Geckskin™ design. The aim of TEL researchers, however, is to do just the opposite — they are using FEA to find an integrated circuit design capable of withstanding the van der Waals forces exerted on the features, thus minimizing pattern collapse.

The article “Pushing the Limits of Chip Density” from the *IEEE Spectrum* insert, *Multiphysics Simulation*, describes how researchers at TEL used simulation software to optimize the design of integrated circuit features. Using COMSOL Multiphysics, TEL researchers were able to optimize the aspect ratio of the features — i.e. the ratio of the feature’s height to its thickness. TEL researchers created a COMSOL model to help them determine which materials and geometric parameters will give rise to pattern collapse, and which will create a stable design. Turn to page 29 in *Multiphysics Simulation* to read about how TEL researchers were able to successfully utilize simulation to verify and optimize a wide variety of integrated circuit parameters.

- “Pushing the Limits of Chip Density”
- Modeling and Prediction of Line Pattern Collapse, presented at the COMSOL Conference 2012

The basic idea of a MOSFET is to apply a gate voltage to control the drain-to-source resistance and thus the drain current (see image below). At a certain gate-to-source voltage (V_{GS}), and at low drain-to-source voltages (V_{DS}), the drain current is almost linearly dependent on V_{DS}. When V_{DS} increases, the drain current saturates. The level of saturation depends on the gate-to-source voltage and the switching time depends on the mobility of the semiconductor. The higher the mobility of the semiconducting material, the faster the current can be switched on and off.

Semiconductor physics is extremely complicated. Strictly speaking, the Boltzmann equation should be solved with Maxwell’s equations in order to describe the device physics completely. Since this is computationally intractable, the most common approach for modeling semiconductors is to solve a set of drift diffusion equations coupled to Poisson’s equation:

\begin{aligned}

\frac{\partial n}{\partial t}&=\frac{1}{q}\nabla \cdot \mathbf{J_{n}}-R_n \\

\frac{\partial p}{\partial t}&=-\frac{1}{q}\nabla \cdot \mathbf{J_{p}}-R_p \\

\nabla \cdot{} \left(\epsilon \nabla V\right) &= -q(p-n+N_D^+-N_A^-)

\end{aligned}

\frac{\partial n}{\partial t}&=\frac{1}{q}\nabla \cdot \mathbf{J_{n}}-R_n \\

\frac{\partial p}{\partial t}&=-\frac{1}{q}\nabla \cdot \mathbf{J_{p}}-R_p \\

\nabla \cdot{} \left(\epsilon \nabla V\right) &= -q(p-n+N_D^+-N_A^-)

\end{aligned}

Here *n* is the number density of electrons, *p* is the number density of holes, *V* is the electrostatic potential, *R _{n}* is the electron recombination rate,

As we recently announced, a dedicated product for modeling semiconductor devices is now available within the COMSOL platform. The Semiconductor Module, as it’s called, allows for detailed analysis of semiconductor device operation at the fundamental physics level. The module is based on the drift-diffusion equations with isothermal or non-isothermal transport models. Two numerical methods are provided: the finite volume method with Scharfetter-Gummel upwinding and a Galerkin least-squares stabilized finite element method. The module provides an easy-to-use interface for analyzing and designing semiconductor devices, greatly simplifying the task of device simulation on the COMSOL platform.

Models for semiconducting and insulating materials in addition to boundary conditions for ohmic contacts, Schottky contacts, and gates are provided as dedicated features within the Semiconductor Module. The module includes enhanced functionality for modeling electrostatics. System level and mixed device simulations are enabled through an interface for electrical circuits with SPICE import capability.

The Semiconductor Module is useful for simulating a range of practical devices. The built-in Model Library contains a suite of models designed to provide straightforward instruction and demonstrate how to use the interface to simulate your own devices. The Semiconductor Module is particularly relevant for simulating transistors including bipolar, metal semiconductor field-effect transistors (MESFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), Schottky diodes, thyristors, and P-N junctions.

The Semiconductor Module could hence be used to investigate the device characteristics of graphene-based semiconductors similar to the ones explained in the paper referenced at the beginning of this blog post.

Over the past few months, in the previous four posts of our blog series, we have read lots about the history, applications, and manufacture of graphene. I’ve enjoyed talking about this topic very much — but I’ve only scratched the surface. There are still many sub-topics that haven’t been explored, and I encourage you to keep up with the latest graphene-related developments in technical magazines and publications. Whether you’re interested in the applications or the manufacture of graphene, COMSOL offers a wide range of products that can provide insight and a better understanding of these processes.