Mechanical Simulation of Electrical Wafer Sort using PAD Over Active Structures in 0.18μm Smart Power Technology

L. Cecchetto1, L. Zullino1, R. Vallauri1, A. Andreini1, L. Redaelli2, P. Anghilieri2, and R. Vettori2
1STMicroelectronics, Agrate Brianza, Italy
2Technoprobe, Agrate Brianza, Italy

The Electrical Wafer Sort (EWS) process is performed on all electronic devices at the end of the silicon diffusion steps to verify IC functionality. This process is performed by probing ICs with suitable tips on a flat metal surface (PAD).

A mechanical simulation feasibility of EWS process is presented here. In most advanced technologies, in order to optimize the area consumption, PAD Over Active (POA) structures have been introduced. Active circuitry is therefore designed below the probing area with potential stress-induced problems.

Good agreement between mechanical simulations and experimental data has been detected evaluating the probe mark and probe force. Finally, the stress on several three dimensional POA structures has been simulated to evaluate critical points.