Surface-Trap-Induced Hysteresis in an InAs Nanowire FET, a Density-Gradient Analysis

Application ID: 97361


This tutorial analyzes the hysteresis of the conductance-gate-voltage (G-Vg) curves of an InAs nanowire FET, using the density-gradient theory to add the effect of quantum confinement to the conventional drift-diffusion formulation, without a large increase of computational costs. The hysteresis is caused by the dynamic charging effects of fast and slow semiconductor-oxide interface traps of continuous energy distributions and of both donor and acceptor types. The capture probability is modeled as thermally activated with a barrier height that varies with the trap energy level. The qualitative behavior and the order of magnitude of the computed G-Vg curves under various voltage ramping conditions agree well with simulation and experiment results found in the literature.

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